1. Field of the Invention
The present invention is related to multiplexing signals between a plurality of function blocks and an input/output (I/O) device on a chip.
2. Background Art
Chips are being manufactured that include increasingly more function blocks. The chips communicate with other chips through I/O devices (e.g., pins or pads). While function blocks are becoming smaller, and the chips denser, there is limited area on the chip for the I/O devices. To compensate for the limited area, groups or sets of the function blocks share the I/O devices.
In order to share the I/O devices, a controlling system (e.g., a multiplexer) is used to direct which of the function blocks use the I/O device at a particular time (e.g., during a particular mode of the chip).
In some conventional systems, controlling which of the sets of function blocks transmit or receive signals via the I/O device is done using pairs of multiplexers. One multiplexer is used to output enables from the I/O device and one multiplexer is used to output data from the I/O device. However, a control system can further add to the density of the chip and reduce available space for function blocks. In other systems, signals from at least one other function block can be sent to a semiconductor closest to the I/O device, and that closest semiconductor controls signal transmission. Generally speaking, input signals do not need a multiplexer because the input is simply wired to multiple locations. There is no multiplexing to be done on the input signal itself However, there is a multiplexer on the output enable so that the receiver of the input signal can control the pin direction.
Conventional chips require the function blocks to be close to their respective I/O device. This is because timing of transmitting and receiving signals off the chip through the I/O device is critical for operation. The timing of a transmitted signal should be predictable compared to a specific time or event of a clock signal. This is especially true if the signals are relatively fast (e.g., about 100 MHz or above). Fast signals that are mistimed as compared to a clock controlling a function block receiving the signal can cause operational errors or failure of the chip or a system employing the chip.
Mis-timing during testing of the chip can cause a false error signal. For example, during testing, if a testing system is expecting a desired output during a specified clock cycle and the timing is incorrect, the chip may be designated faulty when it is not.
Chips behave differently depending on process, temperature, and voltage. The same signal can be fast or slow depending on the process, temperature, and voltage for that specific chip. When the slow conditions exist, that is commonly referred to as the worst-case comer. When the best-case conditions exist, that is called the best-case comer. The relationship of a signal's transition relative to a specific clock period must be maintained for both best-case and worst-case timing comers.
Having these above described limitations can substantially reduce flexibility in designing a layout of the chip.
Therefore, what is needed is a chip having a control device that can control input and output signals between function blocks and an I/O device that does not require the function blocks being controlled to be in any particular location on the chip.